1. Field of the Invention
The present invention relates to substrate modeling. More particularly, the present invention relates to modeling characteristics of a substrate using doping profiles.
2. Description of the Related Art
Integrated circuits are typically modeled, or simulated, prior to fabrication. These simulation tools may be used to optimize performance of integrated circuits as well as reduce the likelihood of failure of such circuits after fabrication. Thus, simulation is advantageous since circuits may be easily redesigned without duplicative fabrication costs.
Simulation tools are typically used to model the behavior of transistor devices that are formed on a substrate as well as interconnect lines that connect these devices. However, through the use of such tools, only a portion of the substrate is modeled. By way of example, during simulation of a transistor device formed on a substrate approximately 400 microns thick, a thickness of approximately 0.1 microns is typically modeled. Since net doping levels vary throughout the substrate, modeling only a traction of the substrate yields an inaccurate simulation of the substrate characteristics. Accordingly, it would be desirable if the entire depth of the substrate were modeled.
Further, a substrate is not an ideal medium. Since recently developed fabrication processes permit device feature sizes to be reduced, the frequency of operation for transistor devices has increased with these developments. Similarly, with such a reduction in device feature size, the distance between transistor devices may be reduced. Since noise attenuates with the distance between the source of the noise (e.g., power supply) and the receiver of the noise, this parasitic noise may easily propagate to multiple devices. As a result, this parasitic noise may prevent these transistor devices from operating correctly. More particularly, these negative consequences may be considerable for sensitive semiconductor devices such as MOS transistors. Thus, it would be desirable if substrate modeling could be performed to detect this noise.
Noise may be transferred to the substrate by a circuit formed on the surface of the substrate. This noise transfer may occur at various interfaces between the circuit and the substrate. A circuit typically includes numerous devices connected by conductive interconnect lines. Capacitance as well as resistance between the substrate and an overlying interconnect line or device may create undesirable parasitic effects. As a result, this parasitic noise may be transferred through the substrate to other devices in the circuit. Thus, it would be desirable to model the interface between the substrate and the circuit.
IC substrates, as well as portions of the substrates, are typically doped. By way of example, portions of substrates may be doped to create device elements, such as source and drain diffusion regions. Thus, substrates commonly include multiple layers that contain various net doping levels. In addition, the resistance present in the substrate varies with these net doping levels. These varied resistances affect the current flow throughout the substrate and therefore the performance of integrated circuits formed on the substrate. Thus, it would be desirable if these doping levels could be considered during the substrate modeling.
In view of the above, it would be desirable if a system and method for modeling substrate noise through varying doping levels were developed. In this manner, noise flowing through the substrate as well as between the substrate and devices formed on the substrate, may be modeled and eliminated. Accordingly, a circuit may be designed to eliminate or reduce this noise at the design phase without estimation or fabrication of the circuit.